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1 dual 800ma low quiescent current 2.25mhz high efficiency synchronous buck regulator ISL78228 the ISL78228 is a high efficiency, dual synchronous step-down dc/dc regulator that can deli ver up to 800ma continuous output current per channel. the supply voltage range of 2.75v to 5.5v allows for the use of a 3.3v or 5v input. the current mode control architecture enables very low duty cycle operation at high frequency with fast transient response and excellent loop stability. the ISL78228 operates above the am radio band as well as the 2.25mhz switching frequency, allowing for the use of small, low cost inductors and capacitors. each channel is optimized for generating an output voltage as low as 0.6v. the ISL78228 has a user configurable mode of operation-forced pwm mode and pfm/pwm mode. the forced pwm mode operation reduces noise and rf interference while the pfm mode operation provides high efficiency by reducing switching losses at light loads. in pfm mode of operation, both channels draw a total quiescent current of only 30a, hence enabling high light load efficiency in order to maximize battery life. the ISL78228 offers a 1ms power-good (pg) to monitor both outputs at power-up. when shutdown, ISL78228 discharges the outputs capacitor. other features include internal digital soft-start, enable for power sequence, overcurrent protection, and thermal shutdown. the ISL78228 is offered in a 3mmx3mm 10 ld dfn package with 1mm maximum height. the complete converter occupies less than 1.8cm 2 area. the ISL78228 is both aec - q100 rated and fully ts16949 compliant. the ISL78228 is rated for the automotive temperature range (-40c to +105c). features ? internal current mode compensation ? 100% maximum duty cycle for lowest dropout ? selectable forced pwm mode and pfm mode ? external synchronization up to 4mhz ? start-up with pre-biased output ? soft-stop output disc harge during disabled ? internal digital soft-start - 2ms ? power-good (pg) output with 1ms delay ? ts16949 compliant ? aec - q100 tested ? pb-free (rohs compliant) applications ? dc/dc pol modules ?c/p, fpga and dsp power ? rear camera systems ? navigation systems ?infotainment systems figure 1. efficiency characteristics curve output load (a) efficiency (%) 40 50 60 70 80 90 100 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 2.5v out -pfm 1.8v out -pfm 2.5v out -pwm 1.8v out -pwm vin = 5v may 2, 2011 fn7849.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ISL78228 2 fn7849.0 may 2, 2011 typical application l1 2.2h lx1 pgnd fb1 vin en2 pg sync input 2.75v to 5.5v output1 2.5v/800ma c1 10f ISL78228 c2 r2 316k r3 100k 10f c3 10pf l2 2.2h fb2 output2 1.8v/800ma c4 r5 200k r6 100k 10f c5 10pf lx2 pgnd en1 pgnd
ISL78228 3 fn7849.0 may 2, 2011 pin configuration ISL78228 (10 ld 3x3 dfn) top view 2 3 4 1 5 9 8 7 10 6 fb1 en1 vin lx1 nc fb2 en2 pg lx2 sync pad pin descriptions dfn symbol description 1 fb1 the feedback network of the channel 1 regulator. fb1 is the negative input to the transconductance error amplifier. the out put voltage is set by an external resistor divider connected to fb1. with a properly selected divider, the output voltage can be se t to any voltage between the power rail (reduced by converter losses) and th e 0.6v reference. there is an internal compensation to meet a typical application. in addition, the regulator power-good and un dervoltage protection circuitry use fb1 to monitor the channel 1 regulator output voltage. 2 en1 regulator channel 1 enable pin. enable the output, v out1 , when driven to high. shutdown the v out1 and discharge output capacitor when driven to low. do not leave this pin floating. 3 vin input supply voltage. connect 10f ceramic capacitor to power ground. 4 lx1 switching node connection for channel 1. connect to one terminal of inductor for v out1 . 5 nc recommended to connect this pin to the exposed pad. 6 sync mode selection pin. connect to logic high or input voltage vin for pfm mode; connect to logi c low or ground for forced pwm mode. connect to an external function generator for synchronization, and negative edge trigger. do not leave this pin floating. 7 lx2 switching node connection for channel 2. connect to one terminal of inductor for v out2 . 8 pg 1ms timer output. at power-up or en_ hi, this output is a 1ms delayed power-good signal for both the v out1 and v out2 voltages. there is an internal 1m ? pull-up resistor. 9 en2 regulator channel 2 enable pin. enable the output, v out2 , when driven to high. shutdown the v out2 and discharge output capacitor when driven to low. do not leave this pin floating. 10 fb2 the feedback network of the channel 2 regulator. fb2 is th e negative input to the transconductance error amplifier. the ou tput voltage is set by an external resistor divider connected to fb2. with a properly selected divider, the output voltage can be se t to any voltage between the power-rail (reduced by converter losses) and the 0.6v reference. there is an internal compensation to meet a typical application. in addition, the regulator power-good and undervoltage protection circuitry use fb2 to monitor the channel 2 regulator output v oltage. - pad the exposed pad must be connected to pgnd for proper electric al performance. add as much vias as possible for optimal therm al performance. ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL78228arz 8228 -40 to +105 10 ld 3x3 dfn l10.3x3c notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL78228 . for more information on msl please see techbrief tb363 .
ISL78228 4 fn7849.0 may 2, 2011 absolute maximum ratings (reference to gnd) thermal information supply voltage (v in ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v v in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 7v (20ms) en1, en2, pg, sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3v to v in + 0.3v lx1, lx2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5v to 6.5v lx1, lx2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5v (100ns) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v (dc) to 7v (20ms) fb1, fb2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 2.7v esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . . . 3kv machine model (tested per jesd-a115-a) . . . . . . . . . . . . . . . . . . . 300v charge device model (tested per jesd22-c101c). . . . . . . . . . . . . . . 2kv latch up (tested per jesd78c; class ii, level a) . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 10 ld 3x3 dfn package (notes 4, 5) . . . . . . 49 4 storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions v in supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.75v to 5.5v load current range per channel . . . . . . . . . . . . . . . . . . . . . 0ma to 800ma ambient temperature range . . . . . . . . . . . . . . . . . . . . . . .-40c to +105c junction temperature range . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications unless otherwise noted, all parameter limits ar e established over the recommended operating conditions: t a = -40c to +105c, v in = 2.75v to 5.5v, en1 = en2 = v in , sync = 0v, l = 2.2h, c 1 = 10f, c 2 = c 4 = 10f, i out1 =i out2 = 0a to 800ma. (typical values are at t a = +25c, v in = 3.6v). boldface limits apply over the operating temperature range, -40c to +105c. parameter symbol test conditions min (note 6) typ max (note 6) units input supply v in undervoltage lockout threshold v uvlo rising 2.5 2.75 v falling 2.1 2.4 v quiescent supply current i vin sync = v in , en1 = en2 = v in , no load at the output and no switches switching. vfb1 = vfb2 = 0.7v 30 50 a sync = gnd, en1 = en2 = vin, f s = 2.25mhz, no load at the output 0.1 1 ma shut down supply current i sd v in = 5.5v, en1 = en2 = gnd 6.5 12 a output regulation fb1, fb2 regulation voltage v fb_ 0.590 0.6 0.610 v fb1, fb2 bias current i fb_ vfb = 0.55v 0.1 a line regulation v in = v o + 0.5v to 5.5v (minimal 2.75v, i out = 0a) 0.2 %/v soft-start ramp time cycle 2ms overcurrent protection peak overcurrent limit i pk1 0.95 1.2 1.6 a i pk2 0.95 1.2 1.6 a peak skip limit i skip1 v in = 3.6v 180 250 360 ma i skip2 180 250 360 ma lx1, lx2 p-channel mosfet on-resistance v in = 5.5v, i o = 200ma 180 350 m v in = 2.75v, i o = 200ma 320 450 m ? n-channel mosfet on-resistance v in = 5.5v, i o = 200ma 180 350 m v in = 2.75v, i o = 200ma 320 450 m
ISL78228 5 fn7849.0 may 2, 2011 lx_ maximum duty cycle 100 % pwm switching frequency f s 1.8 2.25 2.7 mhz synchronization range 2.7 4 mhz lx minimum on-time sync = 0 (forced pwm mode) 100 ns soft discharge resistance r dis_ en = low 80 100 130 ? pg output low voltage sinking 1ma, vfb = 0.5v 0.3 v pg pull-up resistor 1m ? internal p good low rising threshold percentage of nominal regulation voltage 88 92 96 % internal p good low falling threshold percentage of nominal regulation voltage 82 89 91 % delay time (rising edge) 1ms internal p good delay time (falling edge) 1 2 s en1, en2, sync logic input low 0.4 v logic input high 1.4 v sync logic input leakage current i sync pulled up to 5.5v 0.1 1 a enable logic input leakage current i en_ 0.1 1 a thermal shutdown 150 c thermal shutdown hysteresis 25 c note: 6. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. te mperature limits established by characterization and are not production tested. electrical specifications unless otherwise noted, all parameter limits ar e established over the recommended operating conditions: t a = -40c to +105c, v in = 2.75v to 5.5v, en1 = en2 = v in , sync = 0v, l = 2.2h, c 1 = 10f, c 2 = c 4 = 10f, i out1 =i out2 = 0a to 800ma. (typical values are at t a = +25c, v in = 3.6v). boldface limits apply over the operating temperature range, -40c to +105c. (continued) parameter symbol test conditions min (note 6) typ max (note 6) units
ISL78228 6 fn7849.0 may 2, 2011 typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v in = 2.75v to 5.5v, en = v in , l 1 = l 2 = 2.2h, c 1 = 10f, c 2 = c 4 = 10f, v out1 = 2.5v, v out2 = 1.8v, i out1 =i out2 = 0a to 800ma. figure 2. efficiency vs load 2.25mhz 3.3v in pwm figure 3. efficiency vs load 2.25mhz 3.3v in pfm figure 4. efficiency vs load 2.25mhz 5v in pwm figure 5. efficiency vs load 2.25mhz 5v in pfm figure 6. power dissipation vs load 2.25mhz 1.8v out pwm figure 7. v out regulation vs load 2.25mhz 1.2v out pfm 40 50 60 70 80 90 100 0.00.10.20.30.40.50.60.7 0.8 1.2v out - pwm 1.5v out - pwm 2.5v out - pwm 1.8v out - pwm output load (a) efficiency (%) 40 50 60 70 80 90 100 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 output load (a) efficiency (%) 0.8 2.5v out - pfm 1.5v out - pfm 1.8v out - pfm 1.2v out - pfm 40 50 60 70 80 90 100 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 output load (a) efficiency (%) 1.2v out - pwm 1.8v out - pwm 2.5v out - pwm 3.3v out - pwm 1.5v out - pwm output load (a) efficiency (%) 40 50 60 70 80 90 100 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 1.5v out - pfm 1.2v out - pfm 2.5v out - pfm 3.3v out - pfm 1.8v out - pfm 0.00 0.05 0.10 0.15 0.20 0.25 0.30 output load (a) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 3.3v in - pfm 5v in - pwm mode power dissipation (w) 3.3v in - pwm mode 5v in - pfm mode 1.17 1.18 1.19 1.20 1.21 1.22 1.23 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 output load (a) output voltage (v) 3.3v v in pfm 5v in pfm mode 5v in pwm mode 3.3v v in pwm
ISL78228 7 fn7849.0 may 2, 2011 figure 8. v out regulation vs load 2.25mhz 1.5v out figure 9. v out regulation vs load 2.25mhz 1.8v out figure 10. v out regulation vs load 2.25mhz 2.5v out figure 11. v out regulation vs load 2.25mhz 3.3v out figure 12. output voltage regulation vs v in 1.8v out pwm mode figure 13. output voltage regulation vs v in 1.8v out pfm mode typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v in = 2.75v to 5.5v, en = v in , l 1 = l 2 = 2.2h, c 1 = 10f, c 2 = c 4 = 10f, v out1 = 2.5v, v out2 = 1.8v, i out1 =i out2 = 0a to 800ma. (continued) 1.50 1.51 1.52 1.53 1.54 1.55 1.56 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 output load (a) output voltage (v) 3.3v v in pwm 5v in pwm mode 5 v in pfm mode 3.3v v in pfm 1.78 1.79 1.80 1.81 1.82 1.83 1.84 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 output load (a) output voltage (v) 3.3v v in pwm 3.3v v in pfm 5 v in pfm mode 5v in pwm mode 2.49 2.50 2.51 2.52 2.53 2.54 2.55 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 output load (a) output voltage (v) 5v v in pfm 5v v in pwm 3.3v v in pwm 3.3v v in pfm 3.30 3.32 3.34 3.36 3.38 3.40 3.42 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 output load (a) output voltage (v) 5v v in pfm 5v v in pwm 1.77 1.78 1.79 1.80 1.81 1.82 1.83 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 input voltage (v) output voltage (v) 0.8a load pwm 0.4a load pwm 0a load pwm 1.77 1.78 1.79 1.80 1.81 1.82 1.83 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 input voltage (v) output voltage (v) 0a load 0.8a load 0.4a load
ISL78228 8 fn7849.0 may 2, 2011 figure 14. steady state operation at no load channel 1 (pwm) figure 15. steady state operation at no load channel 2 (pwm) figure 16. steady state operation at no load channel 1 (pfm) figure 17. steady state operation at no load channel 2 (pfm) figure 18. steady state operation with full load channel 1 figure 19. steady state operation with full load channel 2 typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v in = 2.75v to 5.5v, en = v in , l 1 = l 2 = 2.2h, c 1 = 10f, c 2 = c 4 = 10f, v out1 = 2.5v, v out2 = 1.8v, i out1 =i out2 = 0a to 800ma. (continued) lx1 2v/div v out1 ripple 20mv/div i l1 0.5a/div 500ns/div lx2 2v/div v out2 ripple 20mv/div i l2 0.5a/div 500ns/div lx1 2v/div v out1 ripple 20mv/div i l1 0.5a/div 500ns/div lx2 2v/div v out2 ripple 20mv/div i l2 0.5a/div 500ns/div lx1 2v/div v out1 ripple 20mv/div i l1 0.5a/div 500ns/div lx2 2v/div v out2 ripple 20mv/div i l2 0.5a/div 500ns/div
ISL78228 9 fn7849.0 may 2, 2011 figure 20. load transient channel 1 (pwm) figure 21. load transient channel 2 (pwm) figure 22. load transient channel 1 (pfm) figure 23. load transient channel 2 (pfm) figure 24. soft-start with no load channel 1 (pwm) figure 25. soft-start with no load channel 2 (pwm) typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v in = 2.75v to 5.5v, en = v in , l 1 = l 2 = 2.2h, c 1 = 10f, c 2 = c 4 = 10f, v out1 = 2.5v, v out2 = 1.8v, i out1 =i out2 = 0a to 800ma. (continued) v out1 ripple 20mv/div i l1 0.5a/div 50s/div v out2 ripple 20mv/div i l2 0.5a/div 50s/div lx1 2v/div v out1 ripple 50mv/div i l1 0.5a/div 50s/div lx2 2v/div v out2 ripple 50mv/div i l2 0.5a/div 50s/div en1 2v/div v out1 1v/div i l1 0.5a/div pg 5v/div 50s/div en2 2v/div v out2 0.5v/div i l2 0.5a/div pg 5v/div 50s/div
ISL78228 10 fn7849.0 may 2, 2011 figure 26. soft-start at no load channel 1 (pfm) figure 27. soft-start at no load channel 2 (pfm) figure 28. soft-start at full load channel 1 figure 29. soft-start at full load channel 2 figure 30. soft-discharge shutdown channel 1 figure 31. soft-discharge shutdown channel 2 typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v in = 2.75v to 5.5v, en = v in , l 1 = l 2 = 2.2h, c 1 = 10f, c 2 = c 4 = 10f, v out1 = 2.5v, v out2 = 1.8v, i out1 =i out2 = 0a to 800ma. (continued) il 0.5a/div en1 2v/div v out1 1v/div i l 0.5a/div pg 5v/div 50s/div en2 2v/div v out2 0.5v/div i l2 0.5a/div pg 5v/div 50s/div en1 2v/div v out1 1v/div i l1 0.5a/div pg 5v/div 50s/div en2 2v/div i l2 0.5a/div pg 5v/div 50s/div v out2 0.5v/div en1 5v/div i l1 0.5a/div pg 5v/div 1ms/div v out1 1v/div en2 5v/div i l2 0.5a/div pg 5v/div 1ms/div v out2 0.5v/div
ISL78228 11 fn7849.0 may 2, 2011 figure 32. ch1 steady state operation at no load (pfm) with frequency = 4mhz figure 33. ch1 steady state operation at full load (pfm) with frequency = 4mhz figure 34. ch2 steady state operation at no load (pfm) with frequency = 4mhz figure 35. ch2 steady state operation at full load (pfm) with frequency = 4mhz figure 36. ch1 and ch2 steady state operation at no load (pfm) with frequency = 4mhz figure 37. ch1 and ch2 steady state operation at full load (pfm) with frequency = 4mhz typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v in = 2.75v to 5.5v, en = v in , l 1 = l 2 = 2.2h, c 1 = 10f, c 2 = c 4 = 10f, v out1 = 2.5v, v out2 = 1.8v, i out1 =i out2 = 0a to 800ma. (continued) lx1 2v/div i l1 0.5a/div synch 2v/div 200ns/div v out1 ripple 20mv/div lx1 2v/div i l1 0.5a/div synch 2v/div v out1 ripple 20mv/div 200ns/div lx2 2v/div i l2 0.5a/div synch 2v/div v out2 ripple 20mv/div 200ns/div lx2 2v/div i l2 0.5a/div synch 2v/div v out2 ripple 20mv/div 200ns/div lx1 5v/div lx2 5v/div synch 5v/div v out1 ripple 20mv/div v out2 ripple 20mv/div 100ns/div lx1 5v/div lx2 5v/div synch 5v/div v out1 ripple 20mv/div v out2 ripple 20mv/div 100ns/div
ISL78228 12 fn7849.0 may 2, 2011 figure 38. output short circuit channel 1 figure 39. output short circuit recovery channel 1 figure 40. output short circuit channel 2 figure 41. output short circuit recovery channel 2 figure 42. output current limit vs temperature typical operating performance unless otherwise noted, operating conditions are: t a = +25c, v in = 2.75v to 5.5v, en = v in , l 1 = l 2 = 2.2h, c 1 = 10f, c 2 = c 4 = 10f, v out1 = 2.5v, v out2 = 1.8v, i out1 =i out2 = 0a to 800ma. (continued) phase1 5v/div i l1 0.5a/div pg 5v/div v out1 1v/div 10s/div lx1 5v/div i l1 0.5a/div pg 5v/div v out1 1v/div 500s/div phase2 5v/div i l2 0.5a/div pg 5v/div v out2 1v/div 10s/div lx2 5v/div i l2 0.5a/div pg 5v/div v out2 0.5v/div 500s/div 0 0.4 0.8 1.2 1.6 2.0 2.4 -50 -30 -10 10 50 90 110 temperature (c) output current (a) 20 70 v in 6v i out2 oc v in 6v i out1 oc v in 3.5v i out2 oc v in 3.5v i out1 oc
ISL78228 13 fn7849.0 may 2, 2011 block diagram lx1 csa1 ocp 0.59v 0.09v skip + slope comp soft- start 0.6v eamp comp pwm/pfm logic controller protection driver fb1 0.552v pg sync shutdown vin pgnd oscillator zero-cross sensing bandgap scp 0.3v en1 shutdown 1ms delay 27pf 200k sgnd 3pf 1.6k lx2 csa2 ocp 0.59v 0.09v skip + + slope comp soft- start eamp comp fb2 shutdown vin pgnd zero-cross sensing bandgap scp 0.3v en2 shutdown 27pf 200k 3pf 1.6k thermal shutdown shutdown 1m vin 0.552v 0.6v + pwm/pfm logic controller protection driver + - + - + - + - + - + - + - + - + - + - + - + - + + - - pg1 pg2
ISL78228 14 fn7849.0 may 2, 2011 theory of operation the ISL78228 is a dual 800ma step-down switching regulator optimized for battery-powered or mobile applications. the regulator operates at 2.25mhz fixed switching frequency under heavy load conditions to allow small external inductor and capacitors to be used for minimal printed-circuit board (pcb) area. at light load, the regulator reduces the switching frequency, unless forced to the fixed frequency, to minimize the switching loss and to maximize the battery life. the two channels are in-phase operation. the quiescent current when the outputs are not loaded is typically only 30a . the supply current is typically only 6.5a when the regulator is shut down. pwm control scheme pulling the sync pin low (<0.4v) forces the converter into pwm mode in the next switching cycle re gardless of output current. each of the channels of the ISL78228 employ the current-mode pulse-width modulation (pwm) cont rol scheme for fast transient response and pulse-by-pulse current limiting shown in the ?block diagram? on page 13. the current loop consists of the oscillator, the pwm comparator comp, current sensing circuit, and the slope compensation for the current loop stability. the current sensing circuit consists of the resistance of the p-channel mosfet when it is turned on and the current se nse amplifier csa1 (or csa2 on channel 2). the gain for the curr ent sensing circuit is typically 0.285v/a. the control reference for the current loops comes from the error amplifier eamp of the voltage loop. the pwm operation is initialized by the clock from the oscillator. the p-channel mosfet is turned on at the beginning of a pwm cycle and the current in the mosfet starts to ramp-up. when the sum of the current amplifier csa1 (or csa2) and the compensation slope (0.33v/s) reaches the control reference of the current loop, the pwm comparator comp sends a signal to the pwm logic to turn off the p-mosfet and to turn on the n-channel mosfet. the n-mosfet stays on until the end of the pwm cycle. figure 43 shows the typical operating waveforms during the pwm operation. the dotted lines illustra te the sum of the compensation ramp and the current-sens e amplifier csa-output. the output voltage is regulated by controlling the reference voltage to the current loop. the bandgap circuit outputs a 0.6v reference voltage to the voltage control loop. the feedback signal comes from the v fb pin. the soft-start block only affects the operation during the start-up and will be discussed separately shortly. the error amplifier is a transconductance amplifier that converts the voltage error signal to a current output. the voltage loop is internally compensated with the 27pf and 200k ? rc network. the maximum eamp voltage output is precisely clamped to 0.8v. skip mode pulling the sync pin high (>2.0v) forces the converter into pfm mode. the ISL78228 enters a pulse-skipping mode at light load to minimize the switching loss by reducing the switching frequency. figure 44 illustra tes the skip-mode operation. a zero-cross sensing circuit shown in the ?block diagram? on page 13 monitors the n-mosfet current for zero crossing. when 8 consecutive cycles of the n-mosfet crossing zero are detected, the regulator enters the skip mode. during the 8 detecting cycles, the current in the inductor is allowed to become negative. the counter is reset to zero when the current in any cycle does not cross zero. once the skip mode is entered, the pulse modulation starts being controlled by the skip comparator shown in the ?block diagram? on page 13. each pulse cycle is still synchronized by the pwm clock. the p-mosfet is turned on at the clock and turned off when its current reaches the thre shold of 250ma. as the average inductor current in each cycle is higher than the average current of the load, the output voltage rises cycle over cycle. when the output voltage reaches 1.5% ab ove the nominal voltage, the figure 43. pwm operation waveforms v eamp v csa duty cycle i l v out figure 44. skip mode operation waveforms clock i l v out nominal pfm current limit load current 0 pwm pfm nominal +1.5% 8 cycles
ISL78228 15 fn7849.0 may 2, 2011 p-mosfet is turned off immediately. then the inductor current is fully discharged to zero and st ays at zero. the output voltage reduces gradually due to the load current discharging the output capacitor. when the output voltage drops to the nominal voltage, the p-mosfet will be turned on ag ain at the clock, repeating the previous operations. the regulator resumes normal pwm mode operation when the output voltage drops 1.5% below the nominal voltage. synchronization control the frequency of operation can be synchronized up to 4mhz by an external signal applied to th e sync pin. the falling edge on the sync triggered the rising edge of the pwm on pulse. overcurrent protection csa1 and csa2 are used to monitor output 1 and output 2 channels respectively. the overcurrent protection is realized by monitoring the csa_ output with the ocp threshold logic, as shown in ?block diagram? on page 13. the current sensing circuit has a gain of 0.285v/a, from the p-mosfet current to the csa_output. when the csa_ outp ut reaches the threshold of 590mv, the ocp comparator is tr ipped to turn off the p-mosfet immediately. the overcurrent function protects the switching converter from a shorted output by monitoring the current flowing through the upper mosfets. upon detection of overcurrent condition, the upper mosfet will be immediately turned off and will not be turned on again until the next switching cycle. pg the power-good signal, (pg) monitors both of the output channels. when powering up, the open-collector power-on-reset output holds low for about 1ms after v o1 and v o2 reaches the preset voltages. the pg output also serves as a 1ms delayed power-good signal. if one of the output is disabled, then pg only monitors the active channels. there is an internal 1m ? pull-up resistor. uvlo when the input voltage is below the undervoltage lock out (uvlo) threshold, the regulator is disabled. enable the enable (en1, en2) input allows the user to control the turning on or off of the regulator for purposes such as power-up sequencing. the regulator is enabled, there is typically a 600s delay for waking up the bandgap reference, then the soft start-up begins. soft-start-up the soft-start-up eliminates the in-rush current during the start-up. the soft-start block outputs a ramp reference to both the voltage loop and the current loop. the two ramps limit the inductor current rising speed as well as the output voltage speed so that the output voltage rises in a controlled fashion. at the very beginning of the start-up, the output voltage is less than 0.2v; hence the pwm operating frequency is 1/3 of the normal frequency. in force pwm mode, the ic will continue to start-up in pfm mode to support pre-biased load applications. discharge mode (soft-stop) when a transition to shutdown mode occurs, or the output undervoltage fault latch is set, the outputs discharge to gnd through an internal 100 ? switch. power mosfets the power mosfets are optimize for best efficiency. the on-resistance for the p-mosfet is typically 180m ? and the on-resistance for the n-mosfet is typical 180m ? . 100% duty cycle the ISL78228 features 100% duty cycle operation to maximize the battery life. when the battery voltage drops to a level that the ISL78228 can no longer maintain the regulation at the output, the regulator completely turns on the p-mosfet. the maximum dropout voltage under the 100% duty-cycle operation is the product of the load current and the on-resistance of the p-mosfet. thermal shut-down the ISL78228 has built-in thermal protection. when the internal temperature reaches +150c, the regulator is completely shut down. as the temperature drops to +130c, the ISL78228 resumes operation by stepping through a soft-start-up. applications information output inductor and capacitor selection to consider steady state and transient operation, ISL78228 typically uses a 2.2h output inductor. higher or lower inductor values can be used to optimize the total converter system performance. for example, for higher output voltage 3.3v applications, in order to decrease the inductor current ripple and output voltage ripple, the output inductor value can be increased. the inductor ripple current can be expressed as shown in equation 1: the inductor?s saturation current rating needs be at least larger than the peak current. the isl 78228 protects the typical peak current 1.2a. the saturation current needs be over 1.8a for maximum output current application. table 1. pg en1 en2 pg1 internal pg2 internal pg 00 x x0 01 x 11 10 1 x1 11 1 11 i v o 1 v o v in -------- ? ?? ?? ?? ? lf s ? ------------------------------------ = (eq. 1)
ISL78228 16 fn7849.0 may 2, 2011 ISL78228 uses internal compensa tion network and the output capacitor value is dependent on the output voltage. the ceramic capacitor is recommended to be x5r or x7r. the recommended minimum output capacitor values are shown in table 2 for the ISL78228. in table 2, the minimum output capacitor value is given for different output voltages to make sure the whole converter system is stable. output voltage selection the output voltage of the regula tor can be programmed via an external resistor divider that is used to scale the output voltage relative to the internal reference voltage and feed it back to the inverting input of the error amplifier. refer to ?typical application? on page 2. the output voltage programming resistor, r 2 (or r 5 in channel 2), will depend on the desired output voltage of the regulator. the value for the feedback resistor is typically between 0 ? and 750k ? , as shown in equation 2. let r 3 = 100k ? , then r 2 will be: if the output voltage desired is 0.6v, then r 3 is left unpopulated and short r 2 . for faster response performance, add 47pf in parallel to r 2 . input capacitor selection the main functions of the input capacitor are to provide decoupling of the parasitic inductance and to provide filtering function to prevent the switching current flowing back to the battery rail. one 10f x5r or x7r ceramic capacitor is a good starting point for the input capaci tor selection for both channels. pcb layout recommendation the pcb layout is a very important converter design step to make sure the designed converter wo rks well. for ISL78228, the power loop is composed of the output inductor (l?s), the output capacitor (c out1 and c out2 ) , the lx?s pins, and the gnd pin. it is necessary to make the power loop as small as possible and the connecting traces among them should be direct, short and wide. the switching node of the converter, the lx_ pins, and the traces connected to the node are very noisy, so keep the voltage feedback trace away from these noisy traces. the input capacitor should be placed as closely as possible to the vin pin. the ground of input and output capacitors sh ould be connected as closely as possible. the heat of the ic is mainly dissipated through the thermal pad. maximizing the copper area connected to the thermal pad is preferable. in addition, a solid ground plane is helpful for better emi performance. it is recommended to add at least 5 vias ground connection within the pad for the best thermal relief. table 2. output capacitor value vs v out ISL78228 v out (v) c out (f) l (h) 0.8 10 1.0~2.2 1.2 10 1.0~2.2 1.6 10 1.0~2.2 1.8 10 1.5~3.3 2.5 10 1.5~3.3 3.3 6.8 1.5~4.7 3.6 8.6 1.5~4.7 r 2 r 3 v out v fb ------------ - 1 ? ?? ?? ?? = (eq. 2)
ISL78228 17 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7849.0 may 2, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: ISL78228 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 5/2/11 fn7849.0 initial release
ISL78228 18 fn7849.0 may 2, 2011 package outline drawing l10.3x3c 10 lead dual flat package (dfn) rev 2, 09/09 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.18mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view (4x) 0.10 index area pin 1 pin #1 index area c seating plane base plane 0.08 see detail "x" c c 5 6 6 a b 0.10 c 2 6 10 1 package 0.90 0.20 0.50 2.38 3.00 (10x 0.25) (8x 0.50) 2.38 1.64 (10 x 0.60) 3.00 0.05 0.20 ref 10 x 0.25 10x 0.40 1.64 outline cb max (4x) 0.10 cb 5 m 7. complaint to jedec mo-229-weed-3 except for e-pad dimensions.

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